This invention relates to a differential output driver, and more particular to a differential output driver which is applied to a transmission terminal of a USB (universal Serial Bus) interface.
Generally, a conventional taper buffer, as shown in FIG. 1A, is only a simply digital design without any compensation to the process. Thus, this kind of circuits contributes to the variation of the process greatly. For example, when using a simulation program (e.g. H-spice) to simulate the circuit under the condition that the voltage of PTNT (PMOS set as typical and NMOS set as typical) is 3.3 Volt, the crossover voltage and rise/fall time (Tr/Tf, Tr=Tf) are adjusted as 1.65 Volt and 6n sec respectively. However, under the conditions of the output loading and the output voltage are identical, e.g. PFNS (PMOS set as fast, and NMOS set as slow) and PSNF (PMOS set as slow and NMOS set as fast), the crossover voltage might be altered to range between 1.2 and 2.05 Volt and the specific value of the rise/fall time will becomes larger than 1.1 or smaller that 0.9, e.g. Tr=7n sec, Tf=5n sec and the crossover voltage will also range between 1.2 and 2.05 Volt. When the rise/fall time of the input control signal Din+/Dinxe2x88x92 are set as identical, as shown in FIG. 1B, and the process is set as PTNT, by executing the simulation program (e.g., H-spice), the simulation result is Tr=Tf and the crossover voltage=VDD/2 (as shown in FIG. 1C). When the process is set as PFNS or PSNF, by executing the simulation program (for simulating the error caused by the shift in the process), the simulation result is Tr Tf and the crossover voltage is not VDD/2 any longer (as shown in FIGS. 1D and 1E).
For solving the problem described above, a compensational differential output driver is developed. As shown in FIG. 2, the circuit structure includes a current source, a first current mirror set, a second current mirror set, a first output buffer, and a second output buffer. However, the first current mirror set includes transistors MP1 and MP2. The second current mirror set includes transistors MN1 and MN2. The first output buffer includes transistors MP3 and MN3. And the second output buffer includes transistors MP4 and MN4. Also, the transistors MP1 and MP2 of the first current mirror set have an identical current I which flows through the path 1 constituted by MP1 and MN1, so that the first current mirror set and the second current mirror set can cause an equal current to achieve Vout={overscore (V)}out, as shown in FIG. 1B. Furthermore, the current by the process will not be influenced, so that the situations in FIGS. 1D and 1E will not occur. But this method still has some drawbacks described as followed:
1. Because transistors MP2 and MN2 are respectively provided by the first and the second current mirror sets, the gate voltages thereof must have some particular limitations. If the restriction on Tr/Tf is necessary, the size of the taper buffer in this method will become larger than conventional one. That""s because the gate voltages are respectively not 0 and VDD any longer, so as to need a larger current which results in the bigger size of the taper buffer, generally 3xcx9c4 times or more.
2. For not interfering with the first and the second current mirrors, the transistors MP3, MP4, MN3, and MN4 must relatively become larger for controlling the current, generally two times or more of the transistors MP2 and MN2.
3. Because the current of the transistor MP2 in the current mirror set is larger, the current of the transistor MP1 will also become larger generally. Thus this method needs more area and power.
Because of the technical defects described above, the applicant keeps on carving unflaggingly to develop a xe2x80x9cdifferential output driver devicexe2x80x9d through wholehearted experience and research.
It is an object of the present invention to provide a differential output driver device and system for well matching the rise/fall time (Tr/Tf, Tr=Tf) of the transmission terminal of a differential output driver device and not being interfered by the process.
It is another object of the present invention to provide a differential output driver device and system which are applied to a USB interface for reducing the noise in the process.
In accordance with an aspect of the present invention, a differential output driver for receiving a differential input voltage within a specific range having a first portion of a relatively higher voltage and a second portion of a relatively lower voltage and obtaining an identical voltage variation for output voltages of the first portion and the second portion includes a step-down circuit for receiving the first portion of the relatively higher voltage and lowing the relatively higher voltage to a first output voltage, a step-up circuit for receiving the second potion of the relatively lower voltage and rising the relatively lower voltage to a second output voltage, a first compensation circuit electrically connected to the step-down circuit for providing a first bias to transform the first output voltage into a first compensation voltage, and a second compensation circuit electrically connected to the step-up circuit for providing a second bias to transform the second output voltage into a second compensation voltage, wherein the second compensation voltage and the first compensation voltage have the identical voltage variation value, so as to make the driver generate a periodic output voltage having a substantially regular waveform.
Preferably, the differential output driver is applied to a transmission terminal of a USB (Universal Serial Bus) interface.
Preferably, the first portion of the relatively higher voltage is ranged between 3 and 5 Volts.
Preferably, the second portion of the relatively lower voltage is ranged between 0 and 3 Volts.
Preferably, the step-down circuit includes a first PMOS (P-type Metal-Oxide-Semiconductor) transistor, a first NMOS (N-type Metal-Oxide-Semiconductor) transistor, and a second NMOS transistor.
Certainly, the second NMOS transistor can be a switch.
Certainly the first NMOS includes at least a set of serially connected NMOS transistors.
Certainly, the second NMOS includes at least a set of serially connected NMOS transistors.
Certainly, the first PMOS provides a third bias for cooperating with the relatively higher voltage to actuate the first NMOS transistor to generate the first output voltage by means of a voltage dividing.
Certainly, the third bias can be equivalent to the second bias.
Preferably, the first compensation circuit includes a second PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor.
Certainly, the second PMOS transistor can be a switch.
Certainly, the second PMOS transistor includes at least a set of serially connected PMOS transistors.
Certainly, the third NMOS transistor includes at least a set of serially connected NMOS transistors.
Certainly, the fourth PMOS provides the first bias for cooperating with the first output voltage to actuate the third NMOS transistor to generate the first compensation voltage by means of a voltage dividing.
Preferably, the step-up circuit includes a third PMOS transistor, a fourth PMOS transistor, and a fifth NMOS transistor.
Certainly, the third PMOS transistor can be a switch.
Certainly, the third PMOS transistor includes at least a set of serially connected PMOS transistors.
Certainly, the fourth PMOS transistor includes at least a set of serially connected PMOS transistors.
Certainly, the fifth NMOS provides a fourth bias for cooperating with the relatively lower voltage to actuate the fourth PMOS transistor to generate the second output voltage by means of a voltage dividing.
Certainly, the fourth bias can be equivalent to the first bias.
Preferably, the second compensation circuit includes a fifth PMOS transistor, a sixth PMOS transistor, and a sixth NMOS transistor.
Certainly, the sixth NMOS transistor can be a switch.
Certainly, the fifth PMOS transistor includes at least a set of serially connected PMOS transistors.
Certainly, the sixth PMOS transistor includes at least a set of serially connected PMOS transistors.
Certainly, the fifth PMOS provides the second bias for cooperating with the second output voltage to actuate the sixth PMOS transistor to generate the second compensation voltage by means of a voltage dividing.
Preferably, the fourth bias is equivalent to the first bias.
In accordance with another aspect of the present invention, a differential output driver system including a first differential output driver and a second differential output driver connected in parallel for receiving a first portion of a relatively higher voltage and a second portion of a relatively lower voltage and obtaining for output voltages of the first portion and the second portion an identical voltage variation wherein the first differential output driver includes a first voltage divider for receiving the first portion of the relatively higher voltage and lowing the relatively higher voltage to a first output voltage, and a first compensator electrically connected to the first voltage divider for providing a first bias to transform the first output voltage into a first compensation voltage, and the second differential output driver includes a second voltage divider for receiving the second portion of the relatively lower voltage and rising the relatively lower voltage to a second output voltage, and a second compensator electrically connected to the second voltage divider for providing a second bias to transform the second output voltage into a second compensation voltage, wherein the second compensation voltage and the first compensation voltage have an identical voltage variation value, so as to make the system generate a periodic output voltage set having a substantially regular waveform.
Preferably, the differential output driver system is applied to a transmission terminal of a USB (Universal Serial Bus) interface.
Certainly, the first portion of the relatively higher voltage is ranged between 3 and 5 Volts.
Preferably, the second portion of the relatively lower voltage is ranged between 0 and 3 Volts.
Preferably, the first voltage divider is equivalent to the second voltage divider.
Preferably, the first compensator is equivalent to the second compensator.
Preferably, the first bias is equivalent to the second bias.
Preferably, the output voltages of the first portion and the second portion have a crossover output voltage.
Certainly, the crossover output voltage can be an average of the first portion of the relatively higher voltage and the second portion of the relatively lower voltage.
The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed descriptions and accompanying drawings, in which: